// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

module i2c_mst (
	i2c_0_clock_clk,
	i2c_0_csr_address,
	i2c_0_csr_read,
	i2c_0_csr_write,
	i2c_0_csr_writedata,
	i2c_0_csr_readdata,
	i2c_0_i2c_serial_sda_in,
	i2c_0_i2c_serial_scl_in,
	i2c_0_i2c_serial_sda_oe,
	i2c_0_i2c_serial_scl_oe,
	i2c_0_interrupt_sender_irq,
	i2c_0_reset_sink_reset_n);	

	input		i2c_0_clock_clk;
	input	[3:0]	i2c_0_csr_address;
	input		i2c_0_csr_read;
	input		i2c_0_csr_write;
	input	[31:0]	i2c_0_csr_writedata;
	output	[31:0]	i2c_0_csr_readdata;
	input		i2c_0_i2c_serial_sda_in;
	input		i2c_0_i2c_serial_scl_in;
	output		i2c_0_i2c_serial_sda_oe;
	output		i2c_0_i2c_serial_scl_oe;
	output		i2c_0_interrupt_sender_irq;
	input		i2c_0_reset_sink_reset_n;
endmodule
